VHDL Design (design.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
entity andgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end andgate;
architecture Behavioral of andgate is
begin
Y<= A AND B ;
end Behavioral;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_tb is
-- Port ( );
end and_tb;
architecture Behavioral of and_tb is
--Component name and entity's name must be same
--ports must be same
component andgate is
Port (A,B:in std_logic;
Y: out std_logic );
end component;
--inputs
signal a: std_logic:= '0';
signal b: std_logic:= '0';
--outputs
signal y : std_logic;
begin
uut: andgate PORT MAP(a=>A,b=>B,y=>Y);
--Stimulus Process
stim_proc:process
begin
wait for 10ns;
a<='1';
b<='0';
wait for 10ns;
a<='0';
b<='1';
wait for 10ns;
a<='0';
b<='0';
wait for 10ns;
a<='1';
b<='1';
wait for 10ns;
end process;
end Behavioral;
OUTPUT
