Eda Playground link :- click here
VHDL Design (design.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
-- HS -> HALF SUBTRACTOR
entity HS is
port(
a,b : in std_logic;
diff,borrow : out std_logic);
end HS;
architecture dataflow of HS is
begin
diff <= a xor b;
borrow <= (not(a)) and b;
end dataflow;
VHDL Testbench ( testbench.vhd )
--HALF SUBTRACTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HS_tb is
end HS_tb;
architecture tb of HS_tb is
component HS is
port(
a,b : in std_logic;
diff,borrow : out std_logic);
end HS;
--inputs
signal a,b: std_logic;
--outputs
signal diff,borrow : std_logic;
begin
uut: HS PORT MAP(a,b,diff,borrow );
--Stimulus Process
stim_proc:process
begin
a<='0';
b<='0';
wait for 10ns;
a<='1';
b<='0';
wait for 10ns;
a<='0';
b<='1';
wait for 10ns;
a<='1';
b<='1';
wait for 10ns;
end process;
end tb;
