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VHDL Design (design.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FS = FULL SUBTRACTOR
entity FS is
Port ( a,b,c : in std_logic;
diff,borrow : out std_logic);
end FS;
architecture Behavioral of FS is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
diff<='0';
borrow<='0';
elsif( a='0' and b='0' and c='1')then
diff<='1';
borrow<='1';
elsif( a='0' and b='1' and c='0')then
diff<='1';
borrow<='1';
elsif( a='0' and b='1' and c='1')then
diff<='0';
borrow<='1';
elsif( a='1' and b='0' and c='0')then
diff<='1';
borrow<='0';
elsif( a='1' and b='0' and c='1')then
diff<='0';
borrow<='0';
elsif( a='1' and b='1' and c='0')then
diff<='0';
borrow<='0';
else
diff<='1';
borrow<='1';
end if;
end process;
end Behavioral;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FS_tb is
end FS_tb;
architecture tb of FS_tb is
component FS is
Port ( a,b,c : in std_logic;
diff,borrow : out std_logic);
end component;
--inputs
signal a,b,c: std_logic;
--outputs
signal diff,borrow : std_logic;
begin
uut: FS PORT MAP(a,b,c,diff,borrow);
--Stimulus Process
stim_proc:process
begin
a<='0';
b<='0';
c<='0';
wait for 10ns;
a<='1';
b<='0';
c<='0';
wait for 10ns;
a<='0';
b<='1';
c<='0';
wait for 10ns;
a<='1';
b<='1';
c<='0';
wait for 10ns;
a<='0';
b<='0';
c<='1';
wait for 10ns;
a<='1';
b<='0';
c<='1';
wait for 10ns;
a<='0';
b<='1';
c<='1';
wait for 10ns;
a<='1';
b<='1';
c<='1';
wait for 10ns;
end process;
end tb;
