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VHDL Design (design.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
entity full_adder is
port(
a,b,Cin : IN std_logic;
SUM,CARRY : OUT std_logic);
end full_adder;
architecture dataflow of full_adder is
begin
SUM <= (a xor b) xor Cin;
CARRY <= (a and b) or (a and Cin) or (b and Cin) ;
end dataflow;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity F_adder_tb is
end F_adder_tb;
architecture dataflow of F_adder_tb is
component full_adder is
Port (A,B,Cin:in std_logic;
sum,carry: out std_logic );
end component;
--inputs
signal a: std_logic:= '0';
signal b: std_logic:= '0';
signal cin: std_logic:= '0';
--outputs
signal sum,carry : std_logic;
begin
uut: full_adder PORT MAP(a=>A,b=>B,cin=>Cin,sum=>SUM,carry=>CARRY);
--Stimulus Process
stim_proc:process
begin
wait for 10ns;
a<='1';
b<='0';
cin<='0';
wait for 10ns;
a<='0';
b<='1';
cin<='0';
wait for 10ns;
a<='0';
b<='0';
cin<='1';
wait for 10ns;
a<='1';
b<='1';
cin<='0';
wait for 10ns;
a<='0';
b<='1';
cin<='1';
wait for 10ns;
a<='1';
b<='0';
cin<='1';
wait for 10ns;
a<='1';
b<='1';
cin<='1';
wait for 10ns;
end process;
end dataflow;
OUTPUT
