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VHDL Design (design.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is
Port ( a,b,c : in std_logic;
sum,carry : out std_logic);
end full_adder;
architecture Behavioral of full_adder is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
sum<='0';
carry<='0';
elsif( a='0' and b='0' and c='1')then
sum<='1';
carry<='0';
elsif( a='0' and b='1' and c='0')then
sum<='1';
carry<='0';
elsif( a='0' and b='1' and c='1')then
sum<='0';
carry<='1';
elsif( a='1' and b='0' and c='0')then
sum<='1';
carry<='0';
elsif( a='1' and b='0' and c='1')then
sum<='0';
carry<='1';
elsif( a='1' and b='1' and c='0')then
sum<='0';
carry<='1';
else
sum<='1';
carry<='1';
end if;
end process;
end Behavioral;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity F_adder_tb is
end F_adder_tb;
architecture Behavioral of F_adder_tb is
component full_adder is
Port ( a,b,c : in std_logic;
sum,carry : out std_logic);
end component;
--inputs
signal a: std_logic:= '0';
signal b: std_logic:= '0';
signal c: std_logic:= '0';
--outputs
signal sum,carry : std_logic;
begin
uut: full_adder PORT MAP(a=>a,b=>b,c=>c,sum=>sum,carry=>carry);
--Stimulus Process
stim_proc:process
begin
wait for 10ns;
a<='1';
b<='0';
c<='0';
wait for 10ns;
a<='0';
b<='1';
c<='0';
wait for 10ns;
a<='0';
b<='0';
c<='1';
wait for 10ns;
a<='1';
b<='1';
c<='0';
wait for 10ns;
a<='0';
b<='1';
c<='1';
wait for 10ns;
a<='1';
b<='0';
c<='1';
wait for 10ns;
a<='1';
b<='1';
c<='1';
wait for 10ns;
end process;
end Behavioral;
OUTPUT
