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VHDL Design (design.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
entity Half_adder is
port(
a,b : IN std_logic;
sum,carry : OUT std_logic);
end Half_adder;
architecture dataflow of Half_adder is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity H_adder_tb is
end H_adder_tb;
architecture dataflow of H_adder_tb is
component Half_adder is
Port (A,B:in std_logic;
sum,carry: out std_logic );
end component;
--inputs
signal a: std_logic:= '0';
signal b: std_logic:= '0';
--outputs
signal sum,carry : std_logic;
begin
uut: Half_adder PORT MAP(a=>A,b=>B,sum=>sum,carry=>carry);
--Stimulus Process
stim_proc:process
begin
wait for 10ns;
a<='1';
b<='0';
wait for 10ns;
a<='0';
b<='1';
wait for 10ns;
a<='0';
b<='0';
wait for 10ns;
a<='1';
b<='1';
wait for 10ns;
end process;
end dataflow;
OUTPUT
