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VHDL Design (design.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Half adder
entity HA is
Port ( A,B : in STD_LOGIC;
S,C : out STD_LOGIC);
end HA;
architecture dataflow of HA is
begin
S <= A XOR B;
C <= A AND B;
end dataflow;
-- ORGATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ORGATE is
Port ( X,Y : in STD_LOGIC;
Z : out STD_LOGIC);
end ORGATE;
architecture dataflow of ORGATE is
begin
Z <= X OR Y;
end dataflow;
-- FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FAdder is
Port ( a, b, c : in STD_LOGIC;
s, ca : out STD_LOGIC);
end FAdder;
architecture structural of FAdder is
component HA is
Port ( A,B : in STD_LOGIC;
S,C : out STD_LOGIC);
end component;
component ORGATE is
Port ( X,Y: in STD_LOGIC;
Z: out STD_LOGIC);
end component;
SIGNAL S0,S1,S2:STD_LOGIC;
begin
U1: HA PORT MAP (a,b,S0,S1);
U2: HA PORT MAP (S0,c,s,S2);
U3: ORGATE PORT MAP (S1,S2,ca);
end structural;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
entity design is
end design;
architecture tb of design is
component FAdder is
Port ( a, b, c : in STD_LOGIC;
s, ca : out STD_LOGIC);
end component;
signal a: std_logic:= '0';
signal b: std_logic:= '0';
signal c: std_logic:= '0';
signal s : std_logic;
signal ca : std_logic;
begin
uut : FAdder port map( a=>a, b=>b,c=>c, s=>s, ca=>ca);
stim_proc:process
begin
a <= '0';
b <= '0';
c <= '0';
wait for 10 ns;
a <= '0';
b <= '0';
c <= '1';
wait for 10 ns;
a <= '0';
b <= '1';
c <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
c <= '1';
wait for 10 ns;
a <= '1';
b <= '0';
c <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
c <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
c <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
c <= '1';
wait for 10 ns;
end process;
end tb;
OUTPUT
