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VHDL Design (design.vhd )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;
architecture dataflow of full_adder_vhdl_code is
begin
S <= (A xor B) xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin) ;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;
architecture Behavioral of Ripple_Adder is
-- Full Adder VHDL Code Component Decalaration
component full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
-- Intermediate Carry declaration
signal c1,c2,c3: STD_LOGIC;
begin
-- Port Mapping Full Adder 4 times
FA1: full_adder_vhdl_code port map( A(0), B(0), Cin, S(0), c1);
FA2: full_adder_vhdl_code port map( A(1), B(1), c1, S(1), c2);
FA3: full_adder_vhdl_code port map( A(2), B(2), c2, S(2), c3);
FA4: full_adder_vhdl_code port map( A(3), B(3), c3, S(3), Cout);
end Behavioral;
VHDL Testbench ( testbench.vhd )
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tb_Ripple_Adder IS
END Tb_Ripple_Adder;
ARCHITECTURE behavior OF Tb_Ripple_Adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Ripple_Adder is
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
--Outputs
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Ripple_Adder PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "0110";
B <= "1100";
wait for 100 ns;
A <= "1111";
B <= "1100";
wait for 100 ns;
A <= "0110";
B <= "0111";
wait for 100 ns;
A <= "0110";
B <= "1110";
wait for 100 ns;
A <= "1111";
B <= "1111";
wait;
end process;
END;
