Eda Playground link :- click here
VHDL Design (design.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
-- HS -> HALF SUBTRACTOR
entity HS is
port(
a,b : in std_logic;
diff,borrow : out std_logic);
end HS;
architecture dataflow of HS is
begin
diff <= a xor b;
borrow <= (not(a)) and b;
end dataflow;
-- ORGATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ORGATE is
Port ( X,Y : in STD_LOGIC;
Z : out STD_LOGIC);
end ORGATE;
architecture dataflow of ORGATE is
begin
Z <= X OR Y;
end dataflow;
-- FULL subtractor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FS = FULL SUBTRACTOR
entity FS is
Port ( a, b, c : in STD_LOGIC;
diff, borrow : out STD_LOGIC);
end FS;
architecture structural of FS is
component HS is
port(
a,b : in std_logic;
diff,borrow : out std_logic);
end component;
component ORGATE is
Port ( X,Y: in STD_LOGIC;
Z: out STD_LOGIC);
end component;
SIGNAL S0,S1,S2:STD_LOGIC;
begin
U1: HS PORT MAP (a,b,S0,S1);
U2: HS PORT MAP (S0,c,diff,S2);
U3: ORGATE PORT MAP (S1,S2,borrow);
end structural;
VHDL Testbench ( testbench.vhd )
library IEEE;
use IEEE.std_logic_1164.all;
entity design is
end design;
architecture tb of design is
component FS is
Port ( a, b, c : in STD_LOGIC;
diff, borrow : out STD_LOGIC);
end FS;
--input
signal a,b,c: std_logic;
--output
signal diff,borrow : std_logic;
begin
uut : FS port map( a, b, c, diff, borrow );
stim_proc:process
begin
a<='0';
b<='0';
c<='0';
wait for 10ns;
a<='1';
b<='0';
c<='0';
wait for 10ns;
a<='0';
b<='1';
c<='0';
wait for 10ns;
a<='1';
b<='1';
c<='0';
wait for 10ns;
a<='0';
b<='0';
c<='1';
wait for 10ns;
a<='1';
b<='0';
c<='1';
wait for 10ns;
a<='0';
b<='1';
c<='1';
wait for 10ns;
a<='1';
b<='1';
c<='1';
end process;
end tb;
